1. Technical Field
This invention relates to recovery of data from non-volatile, auxiliary storage and more particularly to phase-locked loops used in data recovery channels for an auxiliary storage device. Still more particularly, the invention relates to a monolithically integrated, all digital phase-locked loop, operable at a nominal data rate for run length limited code recovered on a data recovery channel.
2. Description of the Related Art
Auxiliary storage is bulk memory for a computer that is of large capacity, slow, and inexpensive per unit of data stored. Auxiliary storage devices are usually based upon moving memory devices such as rotating magnetic or optical disks and drums, or upon moving magnetic tape, which may be locally physically altered in magnetic or optical properties to represent data. Locations for physically altered regions are aligned and spaced in tracks to ease location and readback of the data represented by the regions. Ideally, as a track is moved past a readback transducer at a fixed speed, the locations are presented at regular intervals and the physically altered regions are appropriately aligned and spaced to allow generation of equal and evenly spaced electrical pulses for formatting as data.
The conditions of data storage and recovery are rarely ideal and, as a result, data recovery channels must be adapted to overcome difficulties in, among other things, assigning value to each location, or bit cell, in a track on a magnetic media. A bit cell has 1 of 2 binary values, 1 or 0. If a transducer produces a qualified pulse, the bit cell the pulse is associated with must be determined. Shifts of frequency and of phase in the presentation of bit cells have adverse consequences for assigning the value associated to the correct bit cell. Recovery of a bit stream from a physical track requires recovery of the clock used to write the bit stream. The clock should correspond in frequency to the presentation rate for bit cell locations. Physically altered features of the tracks should be centered within the bit cell. However, a number of factors can cause the bit as written to the media to be shifted from its ideal position, resulting in frequency or phase shifts in readback signal generated by the readback transducer.
A magnetic or optical recording channel is designed to accept data for storage and deliver the same on retrieval demand at a later time with reasonable access delay and without errors. Self-clocking modulation codes are employed to ensure an adequate minimum rate of signal transitions for clock synchronization during data retrieval without exceeding the maximum transition storage density of the magnetic or optical medium during data storage. Such modulation codes are run-length-limiting (RLL) codes that represent a one-to-one mapping of binary data into a constrained binary sequence that is then recorded on the recording medium in the form of a modified Non-Return-to-Zero (NRZI) waveform.
In a NRZI waveform, the maximum and minimum number of spaces between consecutive transitions correspond to the maximum and minimum run lengths of zeros between two consecutive ones in the corresponding binary sequence, as is known in the art. Thus, such modulation codes fall within the class of RLL codes characterized by the parameters (d,k) where d represents the minimum and k represents the maximum number of zeros between two consecutive ones in the coded sequence. These codes are the result of a steady evolution of waveform design coupled with improvements in magnetic and optical recording channels, including improved clocking and signal-detection processes.
In a prior art recording channel, the read clocking function is the key to restoring digital data following transition detection. The read clocking function separates the synchronous data clock signal from the self-clocking data signal in the recording channel. It is usually performed by a phase-locked oscillator (PLO), which regenerates the synchronous data clock waveform in response to the flow of self-clocking signal waveform peaks from the magnetic or optical transition detector. Although this phase control loop can be primarily digital, as with a digital phase-locked loop (DPLL), some analog components have been necessary. Even in a DPLL, the digitally-controlled oscillator (DCO) has employed analog components. Ideally, a digital implementation without analog components is desired because it permits an inexpensive and efficient monolithic device to perform accurate read clocking without calibration drift or adjustment.
Phase-locked loops have been used for synchronizing a variable local oscillator with the phase of a received signal and as a consequence have been widely in a number of applications including bit and symbol synchronization. The basic elements of a phase-locked loop (PLL), particularly in a classic analog configuration, have long been well known. A phase-locked loop is a feedback circuit having a phase detector for comparing an exogenous input signal of potentially varying frequency and phase with a reference signal to produce a phase sensitive error signal. In most applications the phase sensitive signal is filtered by a loop filter designed to attenuate signal noise. The filtered phase sensitive signal is then applied to a voltage controlled oscillator (VCO) which in turn generates the reference signal to be fed back to the phase detector.
A phase-locked loop can generally maintain a lock on input signals over a frequency range called a "lock range". The process by which a phase-locked loop locks on input signals within the lock range is called capture. During capture, an analog phase-locked loop goes from a free-running condition to one in which the voltage controlled oscillator locks on to the frequency of the input signal. A number of complications are presented by capture, particularly of an input frequency which is quite close to the free running frequency, which are beyond the scope of this discussion.
In data recovery systems there has been a one-to-one relationship between the detected data and the associated clock. The analog read-back waveform has been processed, bits generated, and a phase-locked loop used to produce a serial data stream. The voltage controlled oscillator has been used to match the clock frequency with the frequency of data being recovered from the channel with 1 clock period being generated for every detected bit.
A number of digital phase-locked loops have been produced since the mid 1970's. Digital circuitry has a number of advantages over analog circuitry in terms of amenability to programming and suitability for monolithic integration. However, for data recovery systems, there are a number of disadvantages in a digital system which depends upon synchronization of the digital PLL local oscillator with the bit stream. First and foremost, voltage controlled oscillators are intrinsically analog devices. The VCO gain and operating points can be variable depending upon manufacturing processes utilized in their construction and can be relatively costly to build and qualify, thus nullifying what otherwise would be advantages of a digital system. Another disadvantage to digital PLLs that use an analog VCO is that any delays from the time the data is sampled to the time the PLL error voltage of the VCO is generated are within the PLL feedback control path. This vastly complicates design and forces tight engineering tolerances in input frequency for the data.
The superior response speed of analog circuitry has tended to exclude use of all digital phase-locked loops from use in data recovery channels for moveable memory. Preferred design in digital phase-locked loops has dictated a sampling rate of from 10 to 15 times, or more, of the bit stream rates for data channels in which the phase-locked loop in to be installed. Such sampling rates have been thought dictated by the need to avoid error resulting from aliasing phenomena resulting from analog to digital converters operating at a sampling frequency at an integer multiple of a frequency. With proposals for data channels having bit stream rates of up to 80 Mbits/sec., sufficiently high sampling rates are not feasible in contemporary semiconductors. Even were sufficiently high operating frequencies obtainable, inordinate amounts of power would be consumed. Even at bit stream rates of 10 MHz, fabricating an all digital phase-locked loop is, with prior art technology a difficult objective.